View PT7C4307WE_9049635.PDF datasheet online --- IC-ON-LINE

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||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||||||||||||||||||||| real - time clock module (i 2 c bus) 2013 - 06 - 0002 pt0 206 - 5 06 / 1 8 /1 3 1 pt7 c43 07 features ? using external 32.768khz quartz crystal ? supports i 2 c - bus's high speed mode (400 khz) ? includes time (h our /m inute /s econd ) and calendar (y ear /m onth /d ate /d ay ) counter functions (bcd code) ? programmable square wave output signal ? 56 - byte, battery - backed , nonvol atile (nv) ram for data storage ? automatic power - fail detect and swit ch circuitry of battery backup ? consumes less than 500na in battery back up mode with oscillator running description the pt7c4307 serial real - time clock is a low - power clock/ calendar with a programmable square - wave output and 56 bytes of nonvolatile ram . address and data are transferred serially via a 2 - wire, bidirectional bus. the clock/calendar provides seconds, minutes, hours, day, date, month, and year information. the dat e at the end of the month is automatically adjusted for months with fewer than 31 days, including corrections for leap year. the clock operates in either the 24 - hour or 12 - hour format with am/pm indicator. the pt7c4307 has a built - in power sense circuit t hat detects power failures and automatically switches to the battery supply. table 1 shows the basic functions of pt7c4307. more details are shown in section: overview of functions. table 1. basic functions of pt7c4307 item function pt7c4307 1 oscillator source: crystal : 32.768khz ? ? ? ? ? ?
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||| |||||||||||| 2013 - 06 - 0002 pt0 206 - 5 06 / 1 8 /1 3 2 pt7 c43 0 7 real - time clock module (i 2 c bus) pin assignment pin description pin no. pi n type description 1 x1 i oscillator circuit input. together with x2, 32.768khz crystal is connected between them. 2 x2 o oscillator circuit output. together with x1, 32.768khz crystal is connected between them. when 32.768khz external input, x2 must be float. 6 scl i serial clock input. scl is used to synchronize data movement on the i 2 c serial interface. 5 sda i/o serial data input/output. sda is the input/output pin for the 2 - wire serial interface. the sda pin is open - drain output and requires an ex ternal pull - up resistor. 7 sqw/out o square wave/output driver. open drain. four frequencies selectable: 32.768k, 8.192k, 4.096k, 1hz when sqwe bit is set to 1. 8 vcc p power. primary power for pt7c4307. 3 vbat p +3v battery power. 4 gnd p ground. x2 vbat gnd vcc sqw/out scl 6 7 8 1 2 3 x1 4 5 sda pt7c4307 dip-8 soic-8
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||| |||||||||||| 2013 - 06 - 0002 pt0 206 - 5 06 / 1 8 /1 3 3 pt7 c43 0 7 real - time clock module (i 2 c bus) function block maximum ratings storage temperature ................................ ................................ ................................ ... - 65 o c to +150 o c ambient temperature with power applied ................................ .......................... - 40 o c to +85 o c supply voltage to ground potential (vcc to gnd) ................................ .............. - 0.3v to +6.5v dc input (all other inputs except vcc & gnd) ................................ .................. - 0.3v to (v cc +0.3v ) dc output voltage (sda, /inta, /intb pins) ................................ .................... - 0.3v to +6.5v dc output current (fout) ................................ ................................ ....................... - 0.3v to (v cc +0.3v ) power dissipatio n ................................ ................................ ................................ ..... 320mw (depend on package) recommended operating conditions part no. symbol description min type max unit pt7c4307 v cc power voltage 4.5 5 5.5 v v bat battery voltage 2 - 3.5 v ih input high level 2.2 - v cc +0.3 v il input low level - 0.3 - 0.8 t a operating temperature - 40 - 85 oc note: stresses greater than those listed under maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indi cated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. counter chain shift registers address decoder address register i /o interface (i 2 c) scl sda pt7c4307 osc time counter ( sec,min,hour,day,date,month,year ) 56 x 8 ram power manager vbat vcc control register sqw/out x1 x2 c d c g 32.768 khz
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||| |||||||||||| 2013 - 06 - 0002 pt0 206 - 5 06 / 1 8 /1 3 4 pt7 c43 0 7 real - time clock module (i 2 c bus) dc electrical characteristics unless otherwise specified, v dd = 4.5 ~ 5.5 v, t a = - 40 c to +85 c sym. item pin condition min typ max unit v cc supply voltage v cc 4.5 5.0 5.5 v v bat supply voltage v batt 2.0 - 3.5 v pf power fail voltage note 4 1.216 ? bat 1.25 ? bat 1.284 ? bat v i cc current consumption v cc o sc on, note 3 - - 1.5 ma osc off, note 1 - - 200 ? bat current consumption v bat osc on, sqw/out off, note 2 - 300 500 na osc on, sqw/out on (32khz) - 480 800 v il low - level input voltage scl - - 0.8 v v ih high - level input voltage scl 2.0 - - v o l low - level output voltage sda i ol = 5ma - - 0.4 v i il input leakage current scl - - 1 ? oz output current when off sda - - 1 ? note: 1. v cc = 5.0v and sda, scl = 5.0v. 2. v cc = 0v, v bat = 3v. 3. scl clocking at max frequency = 100khz. sda pin open, / eosc bit = 0 (oscillator enabled) 4. v pf measured at v bat = 3.0v. ac electrical characteristics sym description value unit v hm rising and falling threshold voltage high 0.8 v cc v v hl rising and falling threshold voltage low 0.2 v cc v signal t f t r v hm v lm
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||| |||||||||||| 2013 - 06 - 0002 pt0 206 - 5 06 / 1 8 /1 3 5 pt7 c43 0 7 real - time clock module (i 2 c bus) over the operating range symbol item min. typ. max. unit f scl scl clock frequency - - 400 khz t su;sta start condition set - up time 0.6 - - ? hd;sta start condition hold time 0.6 - - ? su;dat data set - up time (rtc read/write) 200 - - ns t hd;dat1 dat a hold time (rtc write) 35 - - ns t hd;dat2 data hold time (rtc read) 0 - - ? su;sto stop condition setup time 0.6 - - ? buf bus idle time between a start and stop condition 1.3 - - ? low when scl = "l" 1.3 - - ? high when scl = "h" 0.6 - - ? r rise time for scl and sda - - 0.3 ? f fall time for scl and sda - - 0.3 ? sp * allowable spike time on bus - - 50 ns c b capacitance load for each bus line - - 400 pf * note: only reference for design s sr p t hd;s ta t sp t su;dat t hd;s ta t hd;dat t su;s ta t su;s to scl sda t buf t hd;sta t su;sta f scl t low t high sr s p start condition restart condition stop condition
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||| |||||||||||| 2013 - 06 - 0002 pt0 206 - 5 06 / 1 8 /1 3 6 pt7 c43 0 7 real - time clock module (i 2 c bus) recommended layout for crystal built - in capacitors specifications and recommended external capacitors parameter symbol typ unit build - in capacitors x1 to gnd c g 20 pf x2 to gnd c d 20 pf recommended external capacitors x1 to gnd c 1 4 pf x2 to gnd c 2 4 pf no te : the frequency of crystal can be optimized by external capacitor c 1 and c 2 , for frequency=32.768hz, c 1 and c 2 should meet the equation as below : cpar + [(c 1 +c g )*(c 2 +c d )]/ [(c 1 +c g )+(c 2 +c d )] =c l cpar is all parasitical capacitor between x1 and x2. c l is c rystal s load capacitance. crystal specifications parameter symbol min typ max unit nominal frequency f o - 32.768 - khz series resistance esr - - 70 k ? l - 12.5 - pf note : the crystal, traces and crystal input pins should be isolated from rf generating signals.
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||| |||||||||||| 2013 - 06 - 0002 pt0 206 - 5 06 / 1 8 /1 3 7 pt7 c43 0 7 real - time clock module (i 2 c bus) function description clock function cpu can read or write data i ncluding the year (last two digits), month, date, day, hour, minute, and second. any (two - digit) year that is a multiple of 4 is treated as a leap year and calculated automatically as such until the year 2099. programmable square wave output a square wave output enable bit controls square wave output at pin 7. 4 frequencies are selectable: 1, 4.096k, 8.192k, 32.768k hz. interface with cpu data is read and written via the i 2 c bus interface using two signal lines: scl (clock) and sda (data). since the output of the i/o pin sda is open drain, a pull - up resistor should be used on the circuit board if the cpu output i/o is also open drain. the scl's maximum clock frequency is 400 khz, which supports the i 2 c bus's high - speed mode. oscillator enable/disable oscill ator can be enabled or disabled by /eosc bit. but time count chain does not shut down when the bit is logic 1. ram 56 ? 8 nonvolatile ram are available for customer use. registers allocation of registers addr. (hex) *1 function register definition bit 7 b it 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 00 seconds (00 - 59) /eosc *2 s40 s20 s10 s8 s4 s2 s1 01 minutes (00 - 59) 0 m40 m20 m10 m8 m4 m2 m1 02 hours (00 - 23 / 01 - 12) 0 12, /24 h20 or p , /a h10 h8 h4 h2 h1 03 days of the week (01 - 07) 0 0 0 0 0 w4 w2 w1 0 4 dates (01 - 31) 0 0 d20 d10 d8 d4 d2 d1 05 months (01 - 12) 0 0 0 mo10 mo8 mo4 mo2 mo1 06 years (00 - 99) y80 y40 y20 y10 y8 y4 y2 y1 07 control *3 out *4 0 0 sqwe *5 0 0 rs1 *6 rs0 *6 08~3f ram *7 - - - - - - - - caution points: *1. pt7c4307 uses 6 bits for address. that is if write data to 41h, the data will be written to 01h address register. *2. oscillator enable bit. when this bit is set to 1, oscillator is stopped but time count chain is still active. *3. control register was used to select sqw/out pin output square wave with one of 4 kinds of frequency or dc level. *4. control sqw/out pin output dc level when square wave is disabled. *5. square wave outputs enable at sqw/out pin. *6. square wave output frequency select. *7. pt7c4307 has 56 ? 8 static ram for customer use. it is volatile ram. *8. all bits marked with " 0 " are read - only bits. their value when read is always "0". all bits marked with " - " are customer using space.
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||| |||||||||||| 2013 - 06 - 0002 pt0 206 - 5 06 / 1 8 /1 3 8 pt7 c43 0 7 real - time clock module (i 2 c bus) control and status register addr. (hex) description d7 d6 d5 d4 d 3 d2 d1 d0 07 control out 0 0 sqwe 0 0 rs1 rs0 (default) 0 0 0 0 0 0 1 1 ? out it controls the output level of the sqw/out pin when the square wave output is disabled. out data description read / write 0 when sqwe = 0, sqw/out pin output low. default 1 when sqwe = 0, sqw/out pin output high. ? sqwe (square wave enable) this bit, when set to a logic 1, will enable the oscillator output. the frequency of the square wave output depends upon the value of the rs0 and rs1 bits. with the square wave output set to 1hz, the clock registers update on the falling edge of the square wave. ? rs (rate select) these bits control the frequency of the square wave output when the square wave output has been enabled. rs1, rs0 data sqw output freq. (hz) read / write 00 1 01 4.096k 10 8.192k 11 32.768k default time counter time digit display (in bcd code): ? second digits: range from 00 to 59 and carried to minute digits when incremented from 59 to 00. ? minute digits: range from 00 to 59 and carried to hour digit s when incremented from 59 to 00. ? hour digits: see description on the /12, 24 bit. carried to day and day - of - the - week digits when incremented from 11 p.m. to 12 a.m. or 23 to 00. addr. (hex) description d7 d6 d5 d4 d3 d2 d1 d0 00 seconds /eosc * s40 s20 s1 0 s8 s4 s2 s1 (default) 0 undefined undefined undefined undefined undefined undefined undefined 01 minutes 0 m40 m20 m10 m8 m4 m2 m1 (default) 0 undefined undefined undefined undefined undefined undefined undefined 02 hours 0 12, /24 h20 or p,/a h10 h8 h4 h2 h1 (default) 0 undefined undefined undefined undefined undefined undefined undefined * note: /eosc bit must be written into 0 to start the time count .
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||| |||||||||||| 2013 - 06 - 0002 pt0 206 - 5 06 / 1 8 /1 3 9 pt7 c43 0 7 real - time clock module (i 2 c bus) ? 12, /24 bit this bit is used to select between 12 - hour clock system and 24 - hour clock syste m. 12, /24 data description read / write 0 24 - hour system 1 12 - hour system this bit is used to select between 12 - hour clock operation and 24 - hour clock operation. 12, /24 description hours register 0 24 - hour time display 1 12 - hour time display * be sure to select between 12 - hour and 24 - hour clock operation before writing the time data. days of the week counter the day counter is a divide - by - 7 counter that counts from 01 to 07 and up 07 before starting again from 01. values that correspond to th e day of week are user defined but must be sequential (i.e., if 1 equals sunday, then 2 equals monday, and so on). illogical time and date entries result in undefined operation. addr. (hex) description d7 d6 d5 d4 d3 d2 d1 d0 03 day s of the week 0 0 0 0 0 w4 w2 w1 (default) 0 0 0 0 0 undefined undefined undefined calendar counter the data format is bcd format. ? day digits: range from 1 to 31 (for january, march, may, july, august, october and december). range from 1 to 30 (for april, june, september a nd november ). range from 1 to 29 (for february in leap years). range from 1 to 28 (for february in ordinary years). carried to month digits when cycled to 1. ? month digits: range from 1 to 12 and carried to year digits when cycled to 1. ? year digits: range f rom 00 to 99 and 00, 04, 08, , 92 and 96 are counted as leap years. 24 - hour clock 12 - hour clock 24 - hour clock 12 - hour clock 00 52 ( am 12 ) 12 72 ( pm 12 ) 01 41 ( am 01 ) 13 61 ( pm 01 ) 02 42 ( am 02 ) 14 62 ( pm 02 ) 03 43 ( a m 03 ) 15 63 ( pm 03 ) 04 44 ( am 04 ) 16 64 ( pm 04 ) 05 45 ( am 05 ) 17 65 ( pm 05 ) 06 46 ( am 06 ) 18 66 ( pm 06 ) 07 47 ( am 07 ) 19 67 ( pm 07 ) 08 48 ( am 08 ) 20 68 ( pm 08 ) 09 49 ( am 09 ) 21 69 ( pm 09 ) 10 50 ( am 10 ) 22 70 ( pm 10 ) 1 1 51 ( am 11 ) 23 71 ( pm 11 )
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||| |||||||||||| 2013 - 06 - 0002 pt0 206 - 5 06 / 1 8 /1 3 10 pt7 c43 0 7 real - time clock module (i 2 c bus) addr. (hex) description d7 d6 d5 d4 d3 d2 d1 d0 04 dates 0 0 d20 d10 d8 d4 d2 d1 (default) 0 0 undefined undefined undefined undefined undefined undefined 05 months 0 0 0 m10 m8 m 4 m2 m1 (default) 0 0 0 undefined undefined undefined undefined undefined 06 years y80 y40 y20 y10 y8 y4 y2 y1 (default) undefined undefined undefined undefined undefined undefined undefined undefined note: any registered imaginary time should be rep laced by correct time, otherwise it will cause the clock counter malfunction. i 2 c bus interface overview of i 2 c - bus the i 2 c bus supports bi - directional communications via two signal lines: the sda (data) line and scl (clock) line. a combination of these two signals is used to transmit and receive communication start/stop signals, data signals, acknowledge signals, and so on. both the scl and sda signals are held at high level whenever communications are not being performed. the starting and stopping of co mmunications is controlled at the rising edge or falling edge of sda while scl is at high level. during data transfers, data changes that occur on the sda line are performed while the scl line is at low level, and on the receiving sid e the data is captured while the scl line is at high level. in either case, the data is transferred via the scl line at a rate of one bit per clock pulse. the i 2 c bus device does not include a chip select pin such as is found in ordinary logic devices. instead of using a chip s elect pin, slave addresses are allocated to each device and the receiving device responds to communications only when its slave address matches the slave address in the received data. system configuration all ports connected to the i 2 c bus must be either open drain or open collector ports in order to enable and connections to multiple devices. scl and sda are both connected to the vdd line via a pull - up resistance. consequently, scl and sda are both held at high level when the bus is released (when commun ication is not being performed). fig 1. system configuration master mcu slave rtc other peripheral device v cc sda scl note: when there is only one master, the mcu is ready for driving scl to "h" and r p of scl may not required. r p r p
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||| |||||||||||| 2013 - 06 - 0002 pt0 206 - 5 06 / 1 8 /1 3 11 pt7 c43 0 7 real - time clock module (i 2 c bus) starting and stopping i 2 c bus communications fig 2 . starting and stopping on i 2 c bus 1) start condition, repeated start condition, and stop condition a ) start condition sda level changes from high to low while scl is at high level b ) stop condition sda level changes from low to high while scl is at high level c ) repeated start condition (restart condition) in some cases, the start condition occurs between a previous star t condition and the next stop condition, in which case the second start condition is distinguished as a restart condition. since the required status is the same as for the start condition, the sda level changes from high to low while scl is at high level. 2) data transfers and acknowledge responses during i 2 c - bus communication a) data transfers data transfers are performed in 8 - bit (1 byte) units once the start condition has occurred. there is no limit on the amount (bytes) of data that are transferred bet ween the start condition and stop condition. the address auto increment function operates during both write and read operations. updating of data on the transmitter (transmitting side)'s sda line is performed while the scl line is at low level. the rece iver (receiving side) captures data while the scl line is at high level. *note with caution that if the sda data is changed while the scl line is at high level, it will be treated as a start, restar t, or stop condition.
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||| |||||||||||| 2013 - 06 - 0002 pt0 206 - 5 06 / 1 8 /1 3 12 pt7 c43 0 7 real - time clock module (i 2 c bus) b) data acknowledge resp onse (ack signal) when transferring data, the receiver generates a confirmation response (ack signal, low active) each time an 8 - bit data segment is received. if there is no ack signal from the receiver, it indicates that normal communication has not been established. (this does not include instances where the master device intentionally does not generate an ack signal.) immediately after the falling edge of the clock pulse corresponding to the 8th bit of data on the scl line, the transmitter r eleases the sda line and the receiver sets the sda line to low (= acknowledge) level. after transmitting the ack signal, if the master remains the receiver for transfer of the next byte, the sda is released at t he falling edge of the clock corresponding to the 9th bit of data on the scl line. data transfer resumes when the master becomes the transmitter. when the master is the receiver, if the master does not send an ack signal in response to the last byte sent from the slave, that indicates to the tran smitter that data transfer has ended. at that point, the transmitter continues to release the sda and awaits a stop condition from the master. slave address the i 2 c bus device does not include a chip select pin such as is found in ordinary logic devices. instead of using a chip select pin, slave addresses are allocated to each device. all communications begin with transmitting the [start condition] + [slave address (+ r/w specification)]. the receiving devic e responds to this communication only when the specified slave address it has received matches its own slave address. slave addresses have a fixed length of 7 bits. see table for the details. an r/w bit is added to each 7 - bit slave address during 8 - bit transfers. operation transfer data slave address r / w bit bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 read d1 h 1 1 0 1 0 0 0 1 (= read) write d0 h 0 (= write) i 2 c buss basic transfer format scl from master 1 2 8 9 sda from transmitter (sending side) sda from receiver (receiving side) release sda low active ack signal s start indication p stop indication sr restart indication a rtc acknowledge a master acknowledge
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||| |||||||||||| 2013 - 06 - 0002 pt0 206 - 5 06 / 1 8 /1 3 13 pt7 c43 0 7 real - time clock module (i 2 c bus) 1) write via i 2 c bus 2) read via i 2 c bus a) standard read s l a v e a d d r e s s ( 7 b i t s ) 1 1 0 1 0 0 0 0 w r i t e s l a v e a d d r e s s + w r i t e s p e c i f i c a t i o n a d d r e s s s p e c i f i e s t h e r e a d s t a r t a d d r e s s . ( n ) a d d r . s e t t i n g a s s l a v e a d d r e s s ( 7 b i t s ) 1 1 0 1 0 0 0 1 r e a d s l a v e a d d r e s s + r e a d s p e c i f i c a t i o n d a t a r e a d ( n + 1 ) d a t a i s r e a d f r o m t h e s p e c i f i e d s t a r t a d d r e s s a n d a d d r e s s a u t o i n c r e m e n t . a b i t 7 6 5 4 3 2 1 0 b i t b i t b i t b i t b i t b i t b i t / a p s r 7 6 5 4 3 2 1 0 b i t b i t b i t b i t b i t b i t b i t b i t d a t a r e a d ( n + x ) a d d r e s s a u t o i n c r e m e n t t o s e t t h e a d d r e s s f o r t h e n e x t d a t a t o b e r e a d . a c k n o a c k a a c k a c k a c k a s t a r t s t o p r e s t a r t d a t a r e a d ( n ) d a t a i s r e a d f r o m t h e s p e c i f i e d s t a r t a d d r e s s a n d a d d r e s s a u t o i n c r e m e n t . a 7 6 5 4 3 2 1 0 b i t b i t b i t b i t b i t b i t b i t b i t a c k d a t a t r a n s f e r r e d ( x + 1 b y t e s + a c k n o w l e d g e ) n o t e : l a s t d a t a b y t e i s f o l l o w e d a n o t a c k n o w l e d g e ( / a ) s i g n a l
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||| |||||||||||| 2013 - 06 - 0002 pt0 206 - 5 06 / 1 8 /1 3 14 pt7 c43 0 7 real - time clock module (i 2 c bus) b) simplified read note: 1. the above steps are an example of transfers of one or two bytes only. there is no limit to the number of bytes transferred during actual communications. 2. 49h, 4ah are used as test mode address. cus tomer should not use the addresses. s l a v e a d d r e s s ( 7 b i t s ) 1 1 0 1 0 0 0 1 r e a d s l a v e a d d r e s s + r e a d s p e c i f i c a t i o n d a t a r e a d ( n + 1 ) a b i t 7 6 5 4 3 2 1 0 b i t b i t b i t b i t b i t b i t b i t / a p s 7 6 5 4 3 2 1 0 b i t b i t b i t b i t b i t b i t b i t b i t d a t a r e a d ( n + x ) a c k n o a c k a c k a s t o p s t a r t d a t a r e a d ( n ) n o t e : d a t a i s r e a d f r o m t h e l a s t o n e s r o r e d i n t h e r e g i s t e r p o i n t e r . a 7 6 5 4 3 2 1 0 b i t b i t b i t b i t b i t b i t b i t b i t a c k d a t a t r a n s f e r r e d ( x + 1 b y t e s + a c k n o w l e d g e ) n o t e : l a s t d a t a b y t e i s f o l l o w e d a n o t a c k n o w l e d g e ( / a ) s i g n a l
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||| |||||||||||| 2013 - 06 - 0002 pt0 206 - 5 06 / 1 8 /1 3 15 pt7 c43 0 7 real - time clock module (i 2 c bus) mechanical information we ( 8 - pin soic ) o rdering information part number package code package pt7c4307w e w lead free and green 8 - pin soic note: ? e = pb - free and green ? adding x suffix = t ape /r eel pericom semiconductor corporation ? 1 - 800 - 435 - 2336 ? www.pericom.com pericom reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best possible product. pericom does not assume any responsibility for use of any circuitry described other than the circu itry embodied in pericom product. the company makes no representations that circuitry described herein i s free from patent infringement or other rights, of pericom . min max a 1.350 1.750 a1 0.100 0.250 a2 1.350 1.550 b 0.330 0.510 c 0.170 0.250 d 4.700 5.100 e 3.800 4.000 e1 5.800 6.200 e l 0.400 1.270 0 8 symbol dimensions in millimeters 1.27 bsc note: 1) controlling dimensions in millimeters. 2) ref : jedec ms - 012e/aa

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